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SPT7734
8-BIT, 40 MSPS,175 mW A/D CONVERTER
FEATURES
* * * * * * * * * * Monolithic 40 MSPS Converter 175 mW Power Dissipation On-Chip Track-and-Hold Single +5 V Power Supply TTL/CMOS Outputs 5 pF Input Capacitance Low Cost Tri-State Output Buffers High ESD Protection: 3,500 V Minimum Selectable +3 V or +5 V Logic I/O
APPLICATIONS
* All High-Speed Applications Where Low Power Dissipation is Required * Video Imaging * Medical Imaging * Radar Receivers * IR Imaging * Digital Communications
GENERAL DESCRIPTION
The SPT7734 is a 8-bit monolithic, low cost, ultralow power analog-to-digital converter capable of minimum word rates of 40 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the need for external components. The input drive requirements are minimized due to the SPT7734's low input capacitance of only 5 pF. Power dissipation is extremely low at only 175 mW typical at 40 MSPS with a power supply of +5.0 V. The digital outputs
are +3 V or +5 V, and are user selectable. The SPT7734 has incorporated proprietary circuit design and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7734 is available in 28-lead SOIC and 32-lead small (7 mm square) TQFP packages over the commercial temperature range.
BLOCK DIAGRAM
ADC Section 1 AIN 1:16 Mux T/H
AutoZero CMP
9-Bit SAR 9
9 D8 Overrange D7 (MSB) D6
P1 P2 CLK In Timing . P15 and Control P16
DAC
. .
ADC Section 2
. . .
9
. . .
. . .
ADC Section 15 ADC Section 16 T/H
AutoZero CMP
9
Enable
9-Bit 16:1 Mux/ Error Correction
D5 D4 D3 D2 D1 DO (LSB)
9-Bit SAR 9 DAC
9
Data Vali d
Ref In
Reference Ladder
VREF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages AVDD ......................................................................... +6 V DVDD ........................................................................ +6 V Input Voltages Analog Input .................................. -0.5 V to AVDD +0.5 V VREF ............................................................................ 0 to AVDD CLK Input .................................................................. VDD AVDD - DVDD ............................................................... 100 mV AGND - DGND ................................................... 100 mV Note: Output Digital Outputs ....................................................... 10 mA Temperature Operating Temperature ................................. 0 to +70 C Junction Temperature ......................................... +175 C Lead Temperature, (soldering 10 seconds) ........ +300 C Storage Temperature ................................ -65 to +150 C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T A=TMAX to TMAX, AV DD =DV DD =+5.0 V, V IN =0 to 4 V, f S=40 MSPS, V RHS =4.0 V, V RLS =0.0 V, unless otherwise specified. TEST CONDITIONS TEST LEVEL SPT7734 TYP
PARAMETERS Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Resistance Input Capacitance Input Bandwidth Offset Gain Error Reference Input Resistance Bandwidth Voltage Range VRLS VRHS VRHS - VRLS (VRHF - VRHS) (VRLS - VRLF) Reference Settling Time VRHS VRLS Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits fIN=3.58 MHz fIN=10.3 MHz
MIN 8
MAX
UNITS Bits
IV IV VI VI IV V V V V VI V IV IV V V V V V VI IV IV V V 40 2 VRLS 50
1.0 0.5 Guaranteed VRHS 5.0 250 2.0 2.0 500 150 4.0 90 75 15 20 600
LSB LSB
(Small Signal)
V k pF MHz LSB LSB MHz V V V mV mV
Clock Cycles Clock Cycles
300 100 0 3.0 1.0
2.0 AVDD 5.0
MHz MHz 12 4.0 30
Clock Cycles
ns ps(p-p)
VI VI
7.3 7.2
7.8 7.7
Bits Bits
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ELECTRICAL SPECIFICATIONS
T A=TMAX to TMAX, AV DD =DV DD =+5.0 V, V IN =0 to 4 V, f S=40 MSPS, V RHS =4.0 V, V RLS =0.0 V, unless otherwise specified. PARAMETERS Dynamic Performance Signal-to-Noise Ratio (without Harmonics) fIN=3.58 MHz fIN=10.3 MHz Harmonic Distortion fIN=3.58 MHz fIN=10.3 MHz Signal-to-Noise and Distortion (SINAD) fIN=3.58 MHz fIN=10.3 MHz Spurious Free Dynamic Range Differential Phase Differential Gain Intermodulation Distortion Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage tRISE tFALL Output Enable to Data Output Delay Power Supply Requirements Voltages OVDD DVDD AVDD Currents AIDD DIDD Power Dissipation IOH = 0.5 mA IOL = 1.6 mA 15 pF load 15 pF load 20 pF load, TA = +25 C 50 pF load over temp. TEST CONDITIONS TEST LEVEL MIN SPT7734 TYP MAX UNITS
VI VI 9 Distortion bins from 1024 pt FFT VI VI
46 45 53 53
49 48 57 56
dB dB dB dB
VI VI fIN=1.0 MHz V V V
46 45
49 48 63 0.3 0.3 TBD
dB dB dB Degree % dB V V A A pF V V ns ns ns ns V V V mA mA mW
VI VI VI VI V VI VI V V V V IV IV IV VI VI VI
2.0 -10 -10 +5 3.5 0.4 10 10 10 22 3.0 4.75 4.75 5.0 5.25 5.25 22 23 225 0.8 +10 +10
5.0 5.0 17 18 175
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range.
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Figure 1A: Timing Diagram 1
1 11
3
9
13 17
ANALOG IN
5 7 15
CLOCK IN
SAMPLING CLOCK (Internal)
INVALID
VALID
DATA OUTPUT DATA VALID
1
2
3
4
5
Figure 1B: Timing Diagram 2
tCLK tC tCH CLOCK IN tCL
DATA OUTPUT
Data O
Data 1
Data 2
Data 3
tOD tS DATA VALID tCH tS tCL
Table I - Timing Parameters
DESCRIPTION Conversion Time Clock Period Clock High Duty Cycle Clock Low Duty Cycle Clock to Output Delay (15 pF Load) Clock to DAV
PARAMETERS tC tCLK tCH tCL tOD tS
MIN tCLK 25 40 40
TYP
MAX
UNITS ns ns
50 50 17 10
60 60
% % ns ns
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TYPICAL INTERFACE CIRCUIT Very few external components are required to achieve the stated device performance. Figure 1 shows the typical interface requirements when using the SPT7734 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. Figure 1 - Typical Interface Circuit
Ref In (+4 V) VRHF VRHS VRLS VRLF VIN VIN VCAL CLK IN CLK DAV AVDD AGND DGND* DVDD D8
The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as follows: Table II - Clock Cycles Clock 1 2 3 4 5-15 16 Operation Reference zero sampling Auto-zero comparison Auto-calibrate comparison Input sample 9-bit SAR conversion Data transfer
SPT7734
D0
Interfacing Logics
EN
The 16 phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one ADC section. After 16 clock periods, the timing cycle repeats. The latency from analog input sample to the corresponding digital output is 12 clock cycles. * Since only 16 comparators are used, a huge power savings is realized. * The auto-zero operation is done using a closed loop system that uses multiple samples of the comparators response to a reference zero.
FB1 FB2 +D5
+A5
Enable/Tri-State (Enable = Active Low)
FB3 +A5 AGND DGND +D5
+
10 F +5 V Analog +5 V Analog RTN
*To reduce the possibility of latch-up, avoid connecting the DGND pins of the ADC to the digital ground of the system.
+
10 F +5 V Digital RTN +5 V Digital
* The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. * Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. * The total input capacitance is very low since sections of the converter which are not sampling the signal are isolated from the input by transmission gates. VOLTAGE REFERENCE The SPT7734 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 2, offset and gain errors of less than 2 LSB can be obtained. SPT7734
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NOTES: 1) FB3 is to be located as closely to the device as possible. 2) There should be no additional connections to the right of FB1 and FB2. 3) All capacitors are 0.1 F surface-mount unless otherwise specified. 4) FB1, FB2 and FB3 are 10 H inductors or ferrite beads.
POWER SUPPLIES AND GROUNDING Fairchild suggests that both the digital and the analog supply voltages on the SPT7734 be derived from a single analog supply as shown in figure 1. A separate digital supply should be used for all interface circuitry. Fairchild suggests using this power supply configuration to prevent a possible latchup condition on power up. OPERATING DESCRIPTION The general architecture for the CMOS ADC is shown in the block diagram. The design contains 16 identical successive approximation ADC sections, all operating in parallel, a 16phase clock generator, an 9-bit 16:1 digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC section.
Figure 2 - Ladder Force/Sense Circuit
1 AGND
Figure 3 - Simplified Reference Ladder Drive Circuit Without Force/Sense Circuit
+4.0 V External Reference VRHS (+3.91 V)
90 mV
+ -
2
R/2
VRHF VRHS
R
3
R
4 5 + -
N/C
R
R=30 (typ) All capacitors are 0.01 F
R
VRLS
R
6
VRLF VIN
VRLS (0.075 V) VRLF (AGND) 0.0 V
R
7
75 mV
R/2
All capacitors are 0.01 F
In cases where wider variations in offset and gain can be tolerated, VRef can be tied directly to VRHF and AGND can be tied directly to VRLF as shown in figure 3. Decouple force and sense lines to AGND with a .01 F capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account: The reference ladder circuit shown in figure 3 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS. Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF - VRHS = 2.25 % of (VRHF - VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS - VRLF = 1.9 % of (VRHF - VRLF) (typical). Figure 3 shows an example of expected voltage drops for a specific case. Vref of 4.0 V is applied to VRHF and VRLF is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V) and a 75 mV increase is seen at VRLS (= 0.075 V). ANALOG INPUT VIN is the analog input. The input voltage range is from VRLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See voltage reference section.)
The drive requirements for the analog inputs are very minimal when compared to most other converters due to the SPT7734's extremely low input capacitance of only 5 pF and very high input resistance in excess of 50 k. The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 4. CALIBRATION The SPT7734 uses an auto calibration scheme to ensure 8-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 8-bit accuracy during device operation. This process is completely transparent to the user. Upon power-up, the SPT7734 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 8bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon power-up of 250 sec (for a 40 MHz clock). Once calibrated, the SPT7734 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7734 to remain in calibration. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 5. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times.
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Figure 4 - Recommended Input Protection Circuit
+V AVDD
DIGITAL OUTPUTS The digital outputs (D0-D8) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7734's TTL/CMOS-compatible outputs with the user's logic system supply. The format of the output data (D0-D7) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing EN high. Table III - Output Data Information
ANALOG INPUT +F.S. + 1/2 LSB OVERRANGE D8 1 O O O O OUTPUT CODE D7-D0 1111 1111 1111 111O
D1
Buffer
47 D2
ADC
-V D1 = D2 = Hewlett Packard HP5712 or equivalent
+F.S. -1/2 LSB +1/2 F.S. +1/2 LSB 0.0 V
OOOO OOOO OOOO OOOO OOOO OOOO
(O indicates the flickering bit between logic 0 and 1). Figure 5 - On-Chip Protection Circuit DO NOT CONNECT PINS (DNC)
VDD
120
Analog
There are two pins designated as Do Not Connect (DNC). These pins must be left floating for proper operation of the device. OVERRANGE OUTPUT
120
Pad
The OVERRANGE OUTPUT (D8) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 LSB. When this condition occurs, D8 will switch to logic 1. All other data outputs (D0 to D7) will remain at logic 1 as long as D8 remains at logic 1. This feature makes it possible to include the SPT7734 into higher resolution systems.
CLOCK INPUT The SPT7734 is driven from a single-ended TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance.
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PACKAGE OUTLINES
32-Lead TQFP
INCHES
A B GH
MILLIMETERS MAX 0.355 0.277 0.355 0.277 0.035 0.018 0.057 0.006 0.008 7 0.029 MIN 8.90 6.90 8.90 6.90 0.68 0.30 1.35 0.05 1.00 typ 0.09 0 0.45 0.20 7 0.75 MAX 9.10 7.10 9.10 7.10 0.89 0.45 1.45 0.15
SYMBOL A B C D E F G H I J
I
MIN 0.347 0.269 0.347 0.269 0.027 0.012 0.053 0.002 0.039 typ 0.004 0 0.018
C
D
K L
E
F
J
K L
28-Lead SOIC
SYMBOL
28
MIN
INCHES MAX 0.712 0.012 .050 typ 0.019 0.012 0.100 0.050 0.419 0.299
MILLIMETERS MIN MAX 17.68 0.10 0.00 0.36 0.23 2.03 0.41 10.01 7.39 18.08 0.30 1.27 0.48 0.30 2.54 1.27 10.64 7.59
IH
1
A B C D E F G H I
0.696 0.004 0.014 0.009 0.080 0.016 0.394 0.291
A F B C D E
H
G
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PIN ASSIGNMENTS
PIN FUNCTIONS
28 27 26 25 24 23 22 21 20 19 18 17 16 15 D8 D7 D6 D5 D4 D3 OVDD OGND D2 D1 D0 DNC DNC EN
AGND 1 VRHF 2
Name AGND VRHF VRHS VRLS VRLF VCAL VIN AVDD DVDD DGND CLK
Function Analog Ground Reference High Force Reference High Sense Reference Low Sense Reference Low Force Calibration Reference Analog Input Analog VDD Digital VDD Digital Ground Input Clock fCLK =fs (TTL) Output Enable Tri-State Data Output, (DO=LSB) Tri-State Output Overrange Data Valid Output Digital Output Supply Digital Output Ground Do Not Connect
VRHS 3 N/C 4
VRLS 5 VRLF VIN 6 7
SOIC
AGND 8 VCAL 9
AVDD 10 DVDD 1 1
DGND 12 CLK 13 DAV 14
AGND
AGND
VRHS
31
VRHF
VRLS
32
EN
D6
D8
D7
D0-7
24 23 22 21
25
30
27
29
26
28
VRLF VIN AGND AGND VCAL AVD D AVD D DVDD
1 2 3 4 5 6 7 8
D5 D4 D3 OVDD OGND D2 D1 D0
D8 DAV OVDD OGND DNC
TQFP
20 19 18 17
13
16
14
12
15
10
1 1
ORDERING INFORMATION
PART NUMBER SPT7734SCS SPT7734SCT TEMPERATURE RANGE 0 to +70 C 0 to +70 C PACKAGE TYPE 28L SOIC 32L TQFP
9
DGND
DAV
DNC
DGND
EN
DVDD
CLK
DNC
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
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